1. Field of the Invention
This invention relates to a method for the production of a semiconductor device and more particularly to a method for the production of a semiconductor device possessed of an element separating area.
2. Description of the Prior Art
As one of the methods for element separation in a semiconductor device, the technique which is called LOCOS (local oxidation of silicon) is known. This technique consists in thermally oxidizing selectively a prescribed part of the surface of a silicon substrate by using a silicon nitride layer as a mask for preventing oxidation thereby forming an oxide layer which is used as an element separating area. The oxide layer which is formed in the element separating area is generally referred to as "field oxide layer."
The element separation according to the LOCOS technique, however, incurs the following two problems.
One of the problems resides in what is referred to as "bird's beak." It is a phenomenon such that the silicon substrate, on being thermally oxidized by the LOCOS technique, exposes the edge of the oxidation preventing mask thereof to the invasion by oxygen and consequently suffers a resultant oxide layer of the surface thereof to induce erosion beneath the oxidation preventing mask. The cross-sectional shape of the eroded part resembles the beak of a bird. This fact explains the designation "bird's beak."
Since this bird's beak results in expanding the field oxide layer, the dimensional dilation of the element separating area poses a problem.
The other problem resides in a phenomenon called "thinning effect." This phenomenon consists in the fact that the thickness of the field oxide layer decreases in accordance as the width of the element separating area decreases. This phenomenon arises from the fact that when the size of the opening formed in the oxidation preventing mask for the purpose of supplying oxygen to the element separating area of the silicon substrate is reduced, the amount of the oxygen supplied through the opening is decreased.
Though these problems have been heretofore known, neither the bird's beak nor the thinning produces very serious adverse effects so long as the element has a large size.
These problems gain in conspicuity, however, when not only the element but also the element separating area is miniaturized in consequence of the miniaturization of semiconductor devices.
Since the bird's beak is not easily reduced in size in concert with the miniaturization of the element, it erodes the element forming area and adds to the ratio of reduction of the size of the element forming area. When the width of the element separating area is reduced below 1 .mu.m, the thinning effect gains in conspicuity and the thickness of the field oxide layer possibly decreases below one half of the thickness of the element separating area of a large width.
As the field oxide layer decreases in thickness as described above, the effect of the introduction of an impurity to directly below the field oxide layer for the purpose of preventing the formation of a channel in the parasitic MOS transistor possibly ceases to exist.
As an element separating structure which is incapable of incurring this problem, the structure produced by a method which comprises forming a trench in a silicon substrate and filling this trench with an insulating substance or polycrystalline silicon has been known. Though this method has been heretofore applied to the bipolar transistor LSI which is in need of a deep element separation, the application of this method to the MOS transistor LSI has been advancing because this method induces neither the bird's beak nor the thinning.
Since the MOS transistor LSI does not require such a deep element separation as is necessary for the bipolar transistor LSI, it adopts as a rule the structure called STI (shallow trench isolation) which effects the element separation with a trench of a relatively small depth approximating closely to 1 .mu.m.
Next, the method for element separation by means of the STI will be described.
To begin with, a first thermal oxide layer 102 is formed in a thickness of 10 nm on a silicon substrate 101 and then a silicon nitride layer 103 is formed thereon in a thickness of 150 nm by the CVD technique as illustrated in FIG. 1A. Subsequently, an element separating area S is defined with a window 105 in a resist mask 104.
Thereafter, an opening part 103a is formed by etching the silicon nitride layer 103 and the first thermal oxide layer 102 under the window 105 and, at the same time, a trench 106 is formed in a thickness of about 0.5 .mu.m in the silicon substrate 101 below the opening part 103a by the RIE (reactive ion etching) technique as illustrated in FIG. 1B.
Next, the resist mask 104 is peeled and then the inner wall of the trench 106 is thermally oxidized to form a second thermal oxide layer 107, 50 nm in thickness, along the inner wall as illustrated in FIG. 1C. Then, a silicon oxide layer 108, 1 .mu.m in thickness, is formed throughout the overall area by the CVD technique to fill the trench 106 with the silicon oxide layer 108.
After an appropriate heat treatment, the silicon oxide layer 108 on the silicon nitride layer 103 by the CMP (chemical mechanical polishing) technique or the RIE technique such that this silicon oxide layer 108 remains inside and on the trench 106 as illustrated in FIG. 1D. In this case, the silicon nitride layer 103 is made to function as a CMP stopper layer.
Thereafter, the silicon nitride layer 103 is removed with phosphoric acid as illustrated in FIG. 1E. Subsequently, the first thermal oxide layer 102 on the silicon substrate 101 is removed with hydrofluoric acid.
Next, the surface of the silicon substrate 101 is thermally oxidized to form a third thermal oxide layer (not shown) on the whole surface. Then, an impurity is ion injected into part of the silicon substrate 101 and the injected impurity is thermally activated to form a well (not shown) in the silicon substrate 101. Thereafter, the third thermal oxide layer is removed with hydrofluoric acid.
Thereafter, the surface of the element forming area of the silicon substrate 101 is thermally oxidized to form a gate oxide layer 109, then a gate electrode 110 is formed on the gate oxide layer 109, and subsequently an impurity diffused layer 111 destined to give rise to a source and a drain is formed in the silicon substrate 101 on the opposite sides (in the perpendicular direction to the surface of the paper) of the gate electrode 110 as illustrated in FIG. 1F.
Incidentally, when the treatment with hydrofluoric acid which is performed as described above is repeated several times after the trench 106 has been filled with the silicon oxide layer 108 and the silicon nitride layer 103 has been removed, the part of the silicon oxide layer 108 buried in the trench 106 that protrudes from the silicon substrate 101 is isotropically etched with the hydrofluoric acid. When the isotropic etching is thus effected in the silicon oxide layer 108, a depressed part 121 of such a shape as is illustrated in FIG. 2A is formed in the silicon oxide layer 108 which is buried in the trench 106.
Since this depressed part 121 is formed between the element forming area and the element separating area S, the upper edge (shoulder part) of the trench 106 is inevitably exposed through this depressed part 121. When a voltage is applied to the gate electrode 110 which is formed astride the element separating area S, therefore, an electric field E is concentrated in the shoulder part of the edge of the trench 106 as illustrated in FIG. 2B.
Consequently, the leak current is made to flow readily through the silicon substrate 101 approximating closely to the shoulder part of the trench 106 even when the gate voltage is low. That is to say, a state equivalent to what is produced when a parasitic transistor of a low threshold is formed is assumed, with the result that the MOS transistor will manifest such characteristics as are illustrated in FIG. 3.
To show the results of the determination of the transistor characteristics, the n type MOS transistor acquires such transistor characteristics as illustrated in FIG. 4A and the p type MOS transistor such transistor characteristics as illustrated in FIG. 5A. These characteristics resemble those illustrated in FIG. 14. The characteristic curves of FIG. 4A and FIG. 5A are found to have such changes as are illustrated in FIG. 4B and FIG. 4B. The small peaks appearing in these changes indicate the changes on the borderline between the characteristic curve of the parasitic transistor illustrated in FIG. 14 and the characteristic curve of the standard transistor. Incidentally, the gate electrodes of FIG. 4A and FIG. 5A have sizes such that the ratio of gate length/gate width is 1/10.
The phenomenon in which the threshold voltage is lowered by the parasitic MOS transistor as described above is referred to as "hump."
The method of injecting ions into the shoulder part of the trench 106 for the purpose of allaying the leak current of the parasitic transistor is proposed in B. Davari et al., IEDM, 1988, pp. 92-95. This method, however, inevitably narrows the element forming area because the impurity is diffused not only in the shoulder part of the trench 106 but also in the neighborhood thereof.
Another method has been proposed which comprises rounding the shoulder part of the trench 106 by thermal oxidation thereby allaying the concentration of electric field in the relevant part. In order for the shoulder part of the trench 106 to be rounded, the thermal oxidation must proceed at a temperature approximating closely to 1200.degree. C. At this high temperature, the semiconductor wafer of a large diameter is liable to warp.
Yet another method which comprises using a polycrystalline silicon layer as a stopper layer against CMP and RIE and eventually utilizing this polycrystalline silicon layer per se as a gate electrode was published at C. Chen et al., IEDM 1996 PP.837-840. Since this method requires the ion injection of an impurity for the formation of a well to be performed through the gate electrode and the gate oxide layer, it inevitably exposes the gate oxide layer to damage.
Besides, a method which comprises forming insulating side walls on the lateral surfaces of the silicon oxide layer 108 illustrated in FIG. 1E which protrude from the silicon substrate 101 and enabling the insulating side walls to bury the depressed part 121 is disclosed in Pierre C. Fazan et al., Iedm, 1993, PP. 57-60. This method, however, does not easily form the side walls in a perfectly controlled state because it is required to repress the dispersion of the growth of the insulating layer and the dispersion of the erosion of the insulating layer by etching. Further, since the erosion by etching for the formation of the side walls is carried out before the formation of the gate oxide layer, it is suspected that the projection of ions during the erosion coarsens the surface of the silicon substrate and exerts an adverse effect on the gate oxide layer.